Semiconductor memory, memory system, and method of controlling the same

ABSTRACT

Various embodiments of a semiconductor system, semiconductor memory, and a method of controlling the same are disclosed. In one exemplary embodiment, the semiconductor memory may include a first circuit area configured to perform an operation corresponding to a general operation command and a second circuit area configured to provide the general operation command to the first circuit area. The second circuit area may be configured to determine whether the semiconductor memory selected to perform the operation based on unique identification information and target identification information allocated to the semiconductor memory.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) toKorean Patent Application No. 10-2009-0103579, filed on Oct. 29, 2009,in the Korean Intellectual Property Office, which is incorporated hereinby reference in its entirety as if set forth in full.

BACKGROUND

1. Technical Field

Various embodiments of the present invention relate to semiconductorapparatuses and related methods. In particular, certain embodimentsrelate to a semiconductor memory, a memory system, and a method ofcontrolling the same.

2. Related Art

A memory system may be configured in such a manner that a memorycontroller, such as a central processing unit (CPU) or a graphicprocessing unit (GPU), can control a plurality of memories. To control aplurality of memories, according to one method, the memory systemallocates a channel for each memory and provides an independent commandand an address signal to each memory through the corresponding allocatedchannel. However, allocating a channel to each memory has a disadvantageof increasing the number of channels and may be difficult to apply to anactual memory system.

SUMMARY

Accordingly, there is a need for an improved memory system that canefficiently control a plurality of semiconductor memories.

To attain the advantages and in accordance with the purposes of theinvention, as embodied and broadly described herein, one exemplaryaspect of the present invention may provide a semiconductor memorycomprising a first circuit area configured to perform an operationcorresponding to a general operation command and a second circuit areaconfigured to provide the general operation command to the first circuitarea. The general operation command may be provided from outside of thesecond circuit area. The second circuit area may be configured todetermine whether the semiconductor memory is selected to perform theoperation based on unique identification information and targetidentification information allocated to the semiconductor memory.

In another exemplary aspect of the present invention, a memory systemmay include a memory controller configured to generate an identificationinformation store command, an identification information check command,a general operation command, unique identification information, andtarget identification information. These commands and information may beprovided at predetermined timings. The memory system may further includea plurality of semiconductor memories, each semiconductor memory beingconfigured to store the unique identification information in response tothe identification information store command and check whether thesemiconductor memory is selected based on the target identificationinformation and the unique identification information in response to theidentification information check command. Each semiconductor memory maybe further configured to perform an operation corresponding to thegeneral operation command depending on the check result (e.g., whetheror not the semiconductor is selected).

According to still another exemplary aspect of the invention, asemiconductor memory may include a first circuit area configured toperform an operation corresponding to an operation command and a secondcircuit area configured to use unique identification information andtarget identification information to check whether or not thesemiconductor memory is selected for the operation and provide theoperation command to the first circuit area depending on the checkresult. The operation command uses some of all bits of an address signalrelated to the operation command. In some exemplary aspects, the firstcircuit area may be configured to directly receive a second operationcommand excluding the operation command through a command channel.

Another exemplary aspect of the invention may provide a memory systemincluding a memory controller configured to output an identificationinformation store command, general operation commands comprising a firstoperation command and a second operation command, unique identificationinformation, and target identification information (e.g., atpredetermined timings). The memory system may also include a pluralityof semiconductor memories, where each semiconductor memory is configuredto store the unique identification information in response to theidentification information store command and check whether thesemiconductor memory is selected based on the unique identificationinformation and the target identification information in response to thefirst operation command (e.g., among the general operation commands),and perform an operation corresponding to the first operation commanddepending on the check result. The first operation command may use someof all bits of an address signal related to the first operation command.

In another exemplary aspect, a method of controlling a method systemcomprising a plurality of semiconductor memories is provided. The methodmay include generating an identification information store command andallocating unique identification information to the plurality ofsemiconductor memories, generating an identification information checkcommand and selecting one or more of the plurality of semiconductormemories, and generating a general operation command and commonlyproviding the general command to the plurality of semiconductormemories, after generating the identification information check command.In various exemplary aspects, at least generating the identificationinformation store command and generating an identification informationcheck command is performed by a memory controller controlling theplurality of semiconductor memories.

According to still another exemplary aspect, a method of controlling amemory system comprising a plurality of semiconductor memories mayinclude generating an identification information store command andallocating unique identification information to the plurality ofsemiconductor memories and commonly providing a preset operation commandto the plurality of semiconductor memories, and selecting one or more ofthe semiconductor memories using an address signal generated inaccordance with the preset operation command.

Additional objects and advantages of the invention will be set forth inpart in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention will be realized and attained bymeans of the elements and combinations particularly pointed out in theappended claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory onlyand are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate various embodiments consistentwith the invention and, together with the description, serve to explainthe principles of the invention.

FIG. 1 is a block diagram of a memory system according to one exemplaryembodiment.

FIG. 2 is an exemplary mapping table showing the identificationinformation with respect to a plurality of memory chips and a pluralityof data channel.

FIG. 3 is an exemplary internal block diagram for one of the memorychips shown in FIG. 1.

FIG. 4 is a timing diagram schematically illustrating an exemplarymethod of storing an identification information according to oneembodiment.

FIG. 5 is a timing diagram schematically illustrating an exemplarymethod of selecting a memory chip.

FIG. 6 is a block diagram of a memory system according to anotherembodiment.

FIG. 7 is an exemplary internal block diagram for one of the memorychips shown in FIG. 6.

DETAILED DESCRIPTION

Reference will now be made in detail to the exemplary embodimentsconsistent with the present disclosure, examples of which areillustrated in the accompanying drawings. Wherever possible, the samereference characters will be used throughout the drawings to refer tothe same or like parts.

FIG. 1 is a block diagram schematically illustrating an exemplaryconfiguration of a memory system that is consistent with variousexemplary aspects of the present disclosure. As shown in FIG. 1, amemory system 100 may include a memory controller 110 and a plurality ofmemory chips 120 through 190. Memory system 100 may also include aplurality of data channels DQ for individually and independentlytransferring data between memory controller 110 and each of memory chips120 through 190. Memory system 100 may further include a command and/oraddress channel CMD/ADD for commonly transferring a command signaland/or an address signal between memory controller 110 and each ofmemory chips 120 through 190.

According to one exemplary aspect, memory system 100 may be configuredto assign unique identification information in the plurality of memorychips 120 through 190 so as to selectively operate one or more of theplurality of memory chips 120 through 190.

By way of example, FIG. 2 illustrates mapping of the identificationinformation with respect to the plurality of memory chips 120 through190 and data channels DQ, and the unique identification information maybe assigned according to the configuration shown in FIG. 2. Bydifferently setting the position of a bit having a value of “0” in theunique identification information, the respective memory chips 120through 190 may have unique identification information.

As will be described further herein, memory controller 110 may beconfigured to provide the unique identification information to theplurality of memory chips 120 through 190 through the data channelsDQ<0:7> mapped according to FIG. 2.

Memory controller 110 may be configured to provide each memory chip withan identification information store command for informing the transferof a unique identification information to the memory chip and anidentification information check command for checking whether therespective memory chip is selected or not.

The plurality of memory chips 120 through 190 are configured to storedata transferred through data channels DQ<0:7> as the uniqueidentification information.

The plurality of memory chips 120 through 190 may have configurationsdifference from one another depending on the types of the memory chips.However, the main components for attaining various aspects of thepresent disclosure have the same configuration. Accordingly, memory chip120 is selected from the plurality of memory chips 120 through 190 as anexample and its configuration will be described herein in more detailwith reference to FIGS. 3 through 5.

Referring to FIG. 3, memory chip 120 may be divided into a first circuitarea and a second circuit area. The first circuit area may include aperipheral circuit/memory area 700. The second circuit area may includea command decoder 200, a first storage unit 300, a second storage unit400, an identification information determination unit 500, and a commandtransfer control unit 600.

Command decoder 200 is configured to generate a decoded command CMD_DEC,a first strobe signal ID_STRB, and a second strobe signal ADD_STRB.Decoded command CMD_DEC may be obtained by decoding a command inputtedthrough command channel CMD from memory controller 110. As will bedescribed further herein, decoded command CMD_DEC may include, forexample, an active command ACT, a pre-charge command PCG, a refreshcommand REF, a read command RD, a write command WT or the like.

When the inputted command is an identification information storecommand, command decoder 200 generates first strobe signal ID_STRB. Onthe other hand, when the inputted command is an identificationinformation check command, command decoder 200 generates second strobesignal ADD_STRB.

First storage unit 300 is configured to store data transferred throughdata channel DQ<0:7> as unique identification information ID<0:7> inresponse to first strobe signal ID_STRB. First storage unit 300 mayinclude a plurality of flip-flops F/F configured to store the datatransferred through data channels DQ<0:7> by the unit of bit.

Second storage unit 400 is configured to store an address signaltransferred through address channel ADD<0:7> as target identificationinformation TID<0:7> in response to second strobe signal ADD_STRB.Memory controller 110 uses target identification information TID<0:7> toselect one or more memory chips in which an operation in accordance witha command transferred through the command channel CMD is desired to beperformed.

Identification information determination unit 500 is configured togenerate an identification information confirm signal ID_FLAG usingtarget identification information TID<0:7> from second storage unit 400and unique identification information ID<0:7> from first storage unit300.

Identification information determination unit 500 may include amultiplexer and may be configured to select target identificationinformation TID<0> corresponding to the same sequence as uniqueidentification information having a value of “0” (for example, ID<0>)and output the selected information as an identification informationconfirm signal ID_FLAG.

Identification information determination unit 500 may further include alatch for storing identification information confirm signal ID_FLAG.

Command transfer control unit 600 is configured to provide decodedcommand CMD_DEC to peripheral circuit/memory area 700 in response to theactivated identification information confirm signal ID_FLAG.

Peripheral circuit/memory area 700 is configured to receive dataDQ<0:15>, addresses ADD<0:15>, and decoded command CMD_DEC and performan active operation, a pre-charge operation, a refresh operation, a reador write operation, or the like in accordance with decoded commandCMD_DEC.

In memory system 100 consistent with the present disclosure, memorycontroller 110 provides the mapped unique identification information tothe plurality of memory chips 120 through 190 such that uniqueidentification information ID<0:7> can be set in the respective memorychips 120 through 190.

Referring to FIG. 4, memory controller 110 may commonly provide anidentification information store command ID STORE to the plurality ofmemory chips 120 through 190 through command channel CMD.

Memory controller 110 provides data having the same values as the uniqueidentification information mapped as illustrated in FIG. 2 to respectivememory chips 120 through 190 through independent data channels DQ<0:7>.

Command decoder 200 of each of memory chips 120 through 190 generatesfirst strobe signal ID_STRB in response to identification informationstore command ID STORE.

First storage unit 300 is configured to store the data transferredthrough data channel DQ<0:7> as unique identification informationID<0:7> in response to first strobe signal ID_STRB.

As described above, the series of operations in which uniqueidentification information ID<0:7> is set in respective memory chips 120through 190 may be performed in an initialization operation interval ofmemory system 100.

Then, referring to FIG. 5, memory controller 110 commonly provides anidentification information check command ID CHECK for selecting one ormore of the plurality of memory chips 120 through 190 through commandchannel CMD to memory chips 120 through 190 before outputting a generaloperation command.

Memory controller 110 commonly provides an address signal having thesame value as the target identification information TID through theaddress channel ADD<0:7> to the plurality of memory chips 120 through190.

Command decoder 200 of each of memory chips 120 through 190 generatessecond strobe signal ADD_STRB in response to identification informationcheck command ID CHECK.

Second storage unit 400 stores the address signal transferred throughaddress channel ADD<0:7> as target identification information TID<0:7>in response to second strobe signal ADD_STRB.

Identification information determination unit 500 selects targetidentification information TID<0> corresponding to the same sequence asunique identification information (for example, ID<0>) having a value of“0”, and outputs the selected information as identification informationconfirm signal ID_FLAG.

Since unique identification information ID<0> of memory chip 120 is setto “0” (see FIG. 2) and target identification information TID<0> is “0”,identification information determination unit 500 activates and outputsidentification information confirm signal ID_FLAG.

As illustrated in FIG. 5, when target identification informationTID<0:7>—i.e., an address signal transferred through the address channelADD<0:7>—indicates “00000000,” it means that memory controller 110selected all the memory chips 120 through 190. Therefore, all the memorychips 120 through 190 may activate and output identification informationconfirm signal ID_FLAG.

Memory controller 110 provides a general operation command followed byidentification information check command ID CHECK, for example, apre-charge command PCG to the plurality of memory chips 120 through 190.

Command transfer control unit 600 provides decoded command CMC_DEC—i.e.,pre-charge command PCG—to peripheral circuit/memory area 700 in responseto activated identification information confirm signal ID_FLAG.Therefore, all memory chips 120 through 190 may perform a pre-chargeoperation.

On the other hand, when target identification information TID<0:7>—i.e.,the address signal transferred through the address channelADD<0:7>—indicates “00001111,” it means that memory controller 110selects memory chips 120 through 150 from the plurality of memory chips120 through 190. Consequently, memory chips 120 through 150, among theplurality of memory chips 120 through 190, activate and outputidentification information confirm signal ID_FLAG.

Memory controller 110 provides a general operation command followed byidentification information check command ID CHECK, for example, arefresh command REF to the plurality of memory chips 120 through 190.

Command transfer control unit 600 provides decoded command CMD_DEC—i.e.,refresh command REF—to peripheral circuit/memory area 700 in response toactivated identification information confirm signal ID_FLAG.

Therefore, although refresh command REF is commonly provided to theplurality of memory chips 120 through 190, only memory chips 120 through150 perform a refresh operation.

FIG. 6 illustrates a block diagram of a memory system 101 according toanother exemplary embodiment consistent with the present disclosure. Asshown, memory system 101 may include a memory controller 111 and aplurality of memory chips 121 through 191.

Memory system 101 may include a plurality of data channels DQ forseparately and independently transferring data between memory controller111 and each of memory chips 121 through 191. Memory system 101 mayfurther include a command and/or address channel CMD/ADD for commonlytransferring a command signal and/or an address signal between memorycontroller 111 and each of memory chips 121 through 191.

Memory system 101 of FIG. 6 can assign unique identification informationin the respective memory chips 121 through 191 in substantially the samemanner as memory system 100 of FIG. 1 does.

However, memory system 101 may be different from memory system 100 ofFIG. 1 in that an identification information check command ID CHECK isnot used, but instead target identification information TID is includedin an address signal provided together with a general operation command.Since target identification information TID is included in an addresssignal together with a general operation command, identificationinformation check command ID CHECK need not be used.

For example, among operation commands, an auto-refresh command AREF usesonly some of all bits of an address signal. At this time, the number ofbits not used by auto-refresh command AREF among all the bits of theaddress signal should be equal to or larger than the number of bitsrequired for the unique identification information.

Therefore, memory controller 111 transfers an address signal to theplurality of memory chips 121 through 191, where the address signalincludes target identification information TID in some bits of theaddress signal that are not used by an operation command.

Memory controller 111 is configured to provide an identificationinformation store command ID STORE for informing the transfer of uniqueidentification information to the plurality of memory chips 121 through191.

At this time, the unique identification information may be mapped in thesame manner as illustrated in FIG. 2.

The plurality of memory chips 121 through 191 may have configurationsdifference from one another depending on the types of the memory chips.However, the main components for attaining various aspects of thepresent disclosure have the same configuration. Accordingly, memory chip121 is selected from the plurality of memory chips 121 through 191 as anexample and its configuration will be described herein with reference toFIG. 7.

Referring to FIG. 7, memory chip 121 may be divided into a first circuitarea and a second circuit area. First circuit area may include aperipheral circuit/memory area 701. Second circuit area may include acommand decoder 201, a first storage unit 300, a second storage unit400, an identification information determination unit 500, and a commandtransfer control unit 600.

Command decoder 201 is configured to generate a decoded commandCMD_DEC2, a first strobe signal ID_STRB, and a second strobe signalADD_STRB2. Decoded command CMD_DEC2 may be obtained by decoding acommand provided by memory controller 111.

Decoded command CMD_DEC2 may include a command which uses only some ofall bits of an address signal, for example, an auto-refresh operationAREF.

When the command is an identification information store command, commanddecoder 201 generates first strobe ID_STRB. When the command is acommand which uses some of all bits of an address signal, commanddecoder 201 generates second strobe ADD_STRB2.

Peripheral circuit/memory area 701 is configured to directly receivegeneral operation commands excluding decoded command CMD_DEC2 throughcommand channel CMD, and receive decoded command CMD_DEC2 throughcommand transfer control unit 600.

The other circuit components excluding command decoder 201 andperipheral circuit/memory area 701 may be configured in the same manneras illustrated in FIG. 3.

The series of operations in which unique identification informationID<0:7> is set in the respective memory chips 121 through 191 may beperformed in an initialization operation interval of memory system 101.Then memory controller 111 provides a general operation command, forexample, an auto-refresh operation AREF to the plurality of memory chips121 through 191.

Furthermore memory controller 111 provides an address signal related toauto-refresh command AREF through address channels ADD<0:15> to theplurality of memory chips 121 through 191.

At this time, memory controller 111 transfers an address signal havingthe same value as target identification information TID through addresschannels ADD<0:7> which are not used by auto-refresh command AREF amongaddress channels ADD<0:15>.

Command decoder 121 of each of memory chips 121 through 191 generatessecond strobe signal ADD_STRB2 in accordance with auto-refresh commandAREF.

Second storage unit 400 stores the address signal transferred throughaddress channel ADD<0:7> as target identification information TID<0:7>in response to second strobe signal ADD_STRB2.

Identification information determination unit 500 selects targetidentification information TID<0> corresponding to the same sequence asthe unique identification information (for example, ID<0>) having avalue of “0”, and outputs the selected information as identificationinformation confirm signal ID_FLAG.

Command transfer control unit 600 provides decoded commandCMD_DEC2—i.e., auto-refresh command AREF—to peripheral circuit/memoryarea 701 in response to activated identification information confirmsignal ID_FLAG.

Therefore, the memory chips in which identification information confirmsignal ID_FLAG is activated, among the plurality of memory chips 121through 191, perform an auto-refresh operation.

According to various embodiments of the present disclosure, the uniqueidentification information is set in the plurality of semiconductormemories such that the plurality of semiconductor memories canselectively perform an operation command.

Furthermore, the selection of the semiconductor memories for specificoperation commands and the performance of operation commands by theselected memories can be controlled at the same time.

Throughout the description, including in the claims, the term“comprising a” should be understood as being synonymous with the term“comprising at least one” unless otherwise specified to the contrary.

While certain embodiments have been described above, it will beunderstood to those skilled in the art that the embodiments describedare by way of example only. Accordingly, the device and method describedherein should not be limited based on the described embodiments. Rather,the apparatus described herein should only be limited in light of theclaims that follow when taken in conjunction with the above descriptionand accompanying drawings.

What is claimed is:
 1. A memory system comprising: a memory controllerconfigured to output an identification information store command,general operation commands comprising a first operation command and asecond operation command, unique identification information, and targetidentification information; and a plurality of semiconductor memories,each semiconductor memory being configured to store the uniqueidentification information in response to the identification informationstore command and check whether the semiconductor memory is selectedbased on the unique identification information and the targetidentification information in response to the first operation command,and perform an operation corresponding to the first operation commanddepending on the check result, wherein the first operation command usessome of all bits of an address signal related to the first operationcommand.
 2. The memory system according to claim 1, wherein the memorycontroller is configured to provide the identification information storecommand and the unique identification information to the semiconductormemory in an initialization interval of the semiconductor memory.
 3. Thememory system according to claim 1, wherein the semiconductor memorycomprises: a first circuit area configured to perform operationscorresponding to the first operation command and the second operationcommand; and a second circuit area configured to store the uniqueidentification information, check whether the semiconductor memory isselected based on the unique identification information and the targetidentification information, and provide the first operation command tothe first circuit area depending on the check result.
 4. The memorysystem according to claim 3, wherein the first circuit area comprises aperipheral circuit and memory area.
 5. The memory system according toclaim 3, wherein the first circuit area is configured to directlyreceive the second operation command through a command channel.
 6. Thememory system according to claim 3, wherein the second circuit area isconfigured to receive the unique identification information through adata channel and receive the target identification information throughan address channel.
 7. The memory system according to claim 3, whereinthe second circuit area comprises: a command decoder configured togenerate a first strobe signal in response to the identificationinformation store command, generate a second strobe signal in responseto the first operation command, and decode the first operation command;a first storage unit configured to store the unique identificationinformation in response to the first strobe signal; a second storageunit configured to store the target identification information inresponse to the second strobe signal; an identification informationdetermination unit configured to select one bit of the targetidentification information in accordance with the unique identificationinformation and output the selected bit as an identification informationconfirm signal; and a command transfer control unit configured toprovide the first operation command to the first circuit area inresponse to the identification information confirm signal.